`timescale 1 ns/ 1 ns
module display_tb();


// test vector input registers
reg sys_clk;
reg sys_rst_n;
reg key;
reg [7:0] data;
// wires      
reg  [10:0]  pixel_xpos_w;
reg  [10:0]  pixel_ypos_w;
wire  [23:0]  pixel_data_w;

// assign statements (if any)                       
rgb_display  u_rgb_display(
    .pixel_clk      (sys_clk),
    .adc_clk        (sys_clk),
    .sys_rst_n      (sys_rst_n ),
    .adc_data       (data),
    .key            (key),

    .pixel_xpos     ( pixel_xpos_w ),
    .pixel_ypos     ( pixel_ypos_w ),
    .pixel_data     ( pixel_data_w )
);
    
initial
begin
    sys_clk<=1'b0;
    sys_rst_n<=1'b0;
    key <=1'b0;
    pixel_xpos_w <= 11'd500;
    pixel_ypos_w <= 11'd500;
    #100
    sys_rst_n<=1'b1;
    key <=1'b1;
    data <= 8'b0;
    #100
    key <=1'b0;
    #20000
    key <=1'b1;
    #100
    key <=1'b0;
    #40000
    $stop;
end

always
begin                                                  
    #8 sys_clk=~sys_clk;  
    data <= data+8'b1;
    pixel_xpos_w <= pixel_xpos_w+11'b1;
    pixel_ypos_w <= pixel_ypos_w+11'b1;
    #8 sys_clk=~sys_clk;  
end 
                                              
endmodule

